In certain applications, it is desirable that a differential voltage comparator be capable of accurately responding to a wide range of differential input voltages, including differential voltages that may vary from tens of microvolts to several volts, while operating at a high sampling frequency. Further, in view of the favorable economics of MOS integrated circuits, it is desirable that such circuit performance be achievable with circuitry that can readily be fabricated with such technology.
A problem in achieving such performance with prior art circuitry is described with reference to FIG. 1A. As illustrated in FIG. 1A, a conventional differential voltage comparator comprises resistive load elements 10 and 12 respectively coupled to the drains 22 and 24 of N-channel enhancement-mode MOS transistors 14 and 16. A common current biasing element 18 is coupled to the sources of the MOS transistors 14 and 16 and provides a constant current I to the two transistors. The gate 20 of the MOS transistor 14 comprises a first input to the differential voltage comparator, and the gate 21 of the MOS transistor 16 comprises a second input to the differential voltage comparator. If the values of the resistive load elements 10 and 12 are equal, and the MOS transistors 14 and 16 have perfectly matched electrical characteristics, and the same voltage is applied to the gate 20 as to the gate 21, the differential output voltage VOUT, which is the differential voltage between the drain 22 and the drain 24, will be equal to 0 volts. But when the first input voltage on the gate 20 is greater than the second input voltage on the gate 21, the MOS transistor 14 will be more conductive than the MOS transistor 16, thereby causing a greater portion of the current I to flow through the MOS transistor 14 and its associated resistive load element 10 than through the MOS transistor 16 and its associated resistive load element 12. Consequently, the voltage at the drain 22 will be negative with respect to that of the drain 24. Conversely, when the first input voltage on the gate 20 is less than the second input voltage on the gate 21, the differential output voltage VOUT will be positive.
Certain applications of the differential voltage comparator, such as high-precision (16 bit, for example) analog-to-digital converters, may require a voltage comparison be made of voltages that differ by less than 100 microvolts shortly after a previous voltage comparison of voltages that differ by several volts. It has been observed, however, that a large voltage differential applied to the gates of the source-coupled MOS transistors (such voltage differential being referred to as an overdrive condition) causes the electrical characteristics of the MOS transistors to temporarily become mismatched. More particularly, it is observed that the transistor receiving the greater gate-to-source voltage, and thus conducting the greater amount of channel current, has its threshold voltage temporarily increased. Consequently, if an overdrive condition is followed by a condition wherein the two input voltages are nearly equal, the differential output voltage VOUT will not quickly transition to its final value; but, instead, an unduly long recovery time is observed.
As illustrated in FIG. 1A, the condition just described is simulated with the use of a switch 26. A voltage V2 is applied to one terminal of the switch 26 and a voltage V1 is applied to the other terminal of the switch 26. The voltage V1 is also coupled to the gate 21 of the MOS transistor 16. With the positive power supply voltage VA+ equal to +5.0 volts, the negative power supply voltage VA- equal to -5.0 volts, V1 equal to 0 volts, and V2 equal to +2.0 volts, the problem described above is illustrated by the waveform of FIG. 1B. Prior to time t=0, the switch 26 is set so as to apply the voltage V2 to the gate 20 of the MOS transistor 14, thereby causing that transistor to be more conductive than the MOS transistor 16. For typical transistor characteristics, bias current I, and load resistances (which may be 4,000 ohms, for example), the differential output voltage may be at a negative value of several volts, shown in FIG. 1B as a voltage VL. At time t=0 the common terminal of the switch 26 switches to make a connection with the voltage V1, thereby causing the differential input voltage to become 0 volts. As illustrated in FIG. 1B, the differential output voltage VOUT does not immediately settle at 0 volts; but, instead, goes to a positive voltage which may be greater than 1 millivolt. Subsequently, though, the differential output voltage gradually settles to 0 volts. (Actual devices are, of course, never perfectly matched; accordingly, the differential output voltage in a non-ideal circuit gradually settles to a small, but repeatable, DC offset voltage.)
It is observed experimentally that the recovery time is dependant upon both the duration of the overdrive condition (which may be referred to as "soak time") and the magnitude of the overdrive. Consequently, the rate at which the differential voltage comparator can accurately make successive comparisons--assuming that it may be necessary to make a very sensitive comparison immediately following an overdrive--is limited by the worst case recovery time of the differential voltage comparator. As described in more detail below in the Description of a Preferred Embodiment, this recovery time problem is not a circuit RC time constant problem, but, instead, arises from a temporary imbalance in the electrical characteristics of the source-coupled MOS transistors caused by operating the MOS transistors at different current levels during the overdrive condition.
FIG. 1C illustrates operation of the circuit of FIG. 1A for the circumstance where the voltage V2 is less than that of V1; for example, V1 may be at 0 volts and V2 at -2.0 volts. As expected, due to symmetry of the differential voltage comparator, the differential output voltage waveform after the switch 26 is changed from the voltage V2 to the voltage V1 is similar to that of FIG. 1B, but with opposite voltage polarities.
In accordance with the foregoing, a need exists for a method and circuitry for decreasing the recovery time of an MOS differential voltage comparator. This need is particularly acute in electronic systems such as high-precision analog-to-digital converters requiring comparison rates of 1 kHz or higher.